This week, I finished my invitation design and I am almost done with my program! As I prepare to finish putting together my portfolio, I'm starting to see the amount of time all this "setup" takes. Balancing time spent on final product and immediate assignments has been a struggle for me, but at least my eyes have been opened to how quickly this deadline is approaching. With prom this week, college visits next week, and AP tests coming up, I realize that my final product must be treated as an immediate assignment too.
Last week, I found a website that had level-by-level code and simulations for learning VHDL. I clicked on the very first demo (basic logic gates) and was pretty confused by the code and simulation. After more searching, I've found a site that has really good explanations of IC chips, thoroughly explaining every basic concept I will need to know (http://www.learnabout-electronics.org/Digital/dig21.php). However, I was a bit curious if the use of multiple gates (especially in the NAND case) for lower cost might slow down the process or increase size. I'll see what my mentor has to say!
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